Lithographic projection apparatus (tools) can be used, for example, in the manufacture of integrated circuits (ICs). In such a case, the mask contains a circuit pattern corresponding to an individual layer of the IC, and this pattern can be imaged onto a target portion (e.g. comprising one or more dies) on a substrate (silicon wafer) that has been coated with a layer of radiation-sensitive material (resist). In general, a single wafer will contain a whole network of adjacent target portions that are successively irradiated via the projection system, one at a time. In one type of lithographic projection apparatus, each target portion is irradiated by exposing the entire mask pattern onto the target portion in one go; such an apparatus is commonly referred to as a wafer stepper. In an alternative apparatus—commonly referred to as a step-and-scan apparatus—each target portion is irradiated by progressively scanning the mask pattern under the projection beam in a given reference direction (the “scanning” direction) while synchronously scanning the substrate table parallel or anti-parallel to this direction; since, in general, the projection system will have a magnification factor M (generally <1), the speed V at which the substrate table is scanned will be a factor M times that at which the mask table is scanned. More information with regard to lithographic apparatus as here described can be gleaned, for example, from U.S. Pat. No. 6,046,792, incorporated herein by reference.
In a manufacturing process using a lithographic projection apparatus, a mask pattern is imaged onto a substrate that is at least partially covered by a layer of radiation-sensitive material (resist). Prior to this imaging step, the substrate may undergo various procedures, such as priming, resist coating and a soft bake. After exposure, the substrate may be subjected to other procedures, such as a post-exposure bake (PEB), development, a hard bake and measurement/inspection of the imaged features. This array of procedures is used as a basis to pattern an individual layer of a device, e.g. an IC. Such a patterned layer may then undergo various processes such as etching, ion-implantation (doping), metallization, oxidation, chemo-mechanical polishing, etc., all intended to finish off an individual layer. If several layers are required, then the whole procedure, or a variant thereof, will have to be repeated for each new layer. Eventually, an array of devices will be present on the substrate (wafer). These devices are then separated from one another by a technique such as dicing or sawing. Thereafter, the individual devices can be mounted on a carrier, connected to pins, etc. Further information regarding such processes can be obtained, for example, from the book “Microchip Fabrication: A Practical Guide to Semiconductor Processing”, Third Edition, by Peter van Zant, McGraw Hill Publishing Co., 1997, ISBN 0-07-067250-4, incorporated herein by reference.
The lithographic tool may be of a type having two or more substrate tables (and/or two or more mask tables). In such “multiple stage” devices the additional tables may be used in parallel, or preparatory steps may be carried out on one or more tables while one or more other tables are being used for exposures. Twin stage lithographic tools are described, for example, in U.S. Pat. No. 5,969,441 and WO 98/40791, incorporated herein by reference.
The photolithography masks referred to above comprise geometric patterns corresponding to the circuit components to be integrated onto a silicon wafer. The patterns used to create such masks are generated utilizing CAD (computer-aided design) programs, this process often being referred to as EDA (electronic design automation). Most CAD programs follow a set of predetermined design rules in order to create functional masks. These rules are set by processing and design limitations. For example, design rules define the space tolerance between circuit devices (such as gates, capacitors, etc.) or interconnect lines, so as to ensure that the circuit devices or lines do not interact with one another in an undesirable way.
Of course, one of the goals in integrated circuit fabrication is to faithfully reproduce the original circuit design on the wafer (via the mask). Another goal is to use as much of the semiconductor wafer real estate as possible. As the size of an integrated circuit is reduced and its density increases, however, the CD (critical dimension) of its corresponding mask pattern approaches the resolution limit of the optical exposure tool. The resolution for an exposure tool is defined as the minimum feature that the exposure tool can repeatedly expose on the wafer. The resolution value of present exposure equipment often constrains the CD for many advanced IC circuit designs.
One factor that degrades the overall performance of the lithographic process is aberrations in the projection lens. Indeed, even though current manufacturing processes allow for production of lenses having high quality standards, lens aberrations still exist, which degrade the imaging performance. Furthermore, lenses age over time, and can exhibit an increase in aberrations and/or flare, thereby further degrading the performance of the lens. Accordingly, there is a need for a simple and cost effective method for compensating for lens aberrations and the degradation of lens performance over time.
As explained in detail below, the preferred embodiment of the present invention provides a method and apparatus for compensating for lens aberrations and the degradation of lens performance over time (e.g., lenses typically exhibit a drift the low order components of the aberration signature). However, prior to discussing the present invention, a brief overview of the lithographic process and some currently known optimization techniques are described so as to facilitate the understanding of the present invention. It is noted that as defined herein the term “lens aberration” includes effects due to distortion of lens, defocus, variations in laser wavelength, wafer flatness, and barometric pressure.
FIG. 1 is a block diagram illustrating the basic components of an imaging system 10. Referring to FIG. 1, the imaging system 10 includes an illumination source 12 for illuminating a mask 14 (also known as a reticle). Once passing through the mask, the light passes through a pupil 16 and is captured by the projection lens 18 and projected onto the substrate 20, on which the desired pattern is to be imaged. As can be appreciated from FIG. 1, if aberrations exist in the projection lens of the imaging system, degradations in performance occur.
It is noted that methods for optimizing the source illumination and mask patterns so as to improve the overall printing performance have been disclosed in the prior art. One such method is disclosed in U.S. Pat. Publication No. 2002/01490920 A1 to Rosenbluth et al. Specifically, Rosenbluth discloses a lithographic optimization system that alleges to perform an optimization of source illumination and mask patterns to improve the printing of a given mask pattern. The function of merit utilized by Rosenbluth for determining the optimal combination of the source/mask pattern is the aerial image log-slope at a number of pre-selected points along the border of the pattern geometry. The optimization algorithm appears based on the assumption that the printing of a lithographic pattern is solely determined by the set of diffraction orders collected in the imaging pupil, independent of their location in the pupil plane.
However, while maximizing the aerial image log-slope at selected sampling locations in the pattern enhances the budget/tolerance for exposure variations, commonly referred to as the exposure latitude (EL), it does not help to increase the budget/tolerance for focus variations, commonly referred to as the depth of focus (DOF). Indeed, it is known that patterns that are optimized for EL under in-focus conditions (i.e., at zero DOF) show complementary results compared to patterns that have been optimized for typical process conditions that accommodate for defocus variations. Thus, the optimization routine of Rosenbluth would suffer from this problem.
A further limitation of the optimization process of Rosenbluth is that the effect of a diffraction pattern on the projected image is assumed to be independent of the position of the diffraction orders in the pupil plane. Thus, the Rosenbluth process excludes the modeling of lens aberration effects which act as a pupil plane position dependent wave front modulation affecting the projected image as a function of the exact location of the diffraction pattern in the pupil plane.
Furthermore, it is known that illuminating mask patterns by utilizing off axis illumination (OAI) can enhance the depth of focus for printed images. An example of such applications are selectable diffractive optical elements (DOE) modules, such as Quasar, Dipole or Quadrupole Source illumination elements. Use of such elements can improve the DOF as well as the EL for a given lithographic process. However, such illuminators have predetermined shapes that may or may not produce the optimal possible illumination profile. Currently, there is no method for optimizing such source shape patterns to account for lens aberrations in the projection lens, while also improving both the DOF and the EL for a given lithographic process.
Accordingly, as noted above, there remains a need for a simple and cost effective method for compensating for lens aberrations and the degradation of lens performance over time, which also simultaneously optimizes the DOF performance for a given lithographic process.